SerDes System Designer, Sr. Staff
Synopsys
Ottawa, ON-
Number of positions available : 1
- Salary To be discussed
- Published on July 18th, 2025
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Starting date : 1 position to fill as soon as possible
Description
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are a highly skilled and motivated engineer with a deep technical background in high-speed serial interfaces and a passion for cutting-edge technology. You are adept at modeling, simulation, and analysis, with hands-on experience using MATLAB/Simulink. Your expertise spans high-speed analog and digital design, with a strong foundation in digital communication theory, and digital signal processing. You thrive in cross-disciplinary environments, collaborating seamlessly with analog, digital, and lab teams to solve challenging problems and deliver innovative solutions.
What You’ll Be Doing:
- Developing, updating, and maintaining advanced system-level models for next-generation SerDes transceivers (200Gbps and beyond) using MATLAB/Simulink and other modeling tools.
- Developing novel algorithms and/or improve upon the existing signal processing and detection algorithms (including equalization, clock and data recovery) for high-speed analog and digital circuit implementation, focusing on performance, power efficiency, and area optimization for SoC integration.
- Running comprehensive system simulations to verify design performance across multiple protocols (e.g., OIF, Ethernet) and challenging channel environments.
- Correlating simulated results with silicon measurements, identifying root causes of discrepancies, and collaborating with design teams to implement corrective actions.
- Analyzing link budgets for NRZ and PAM4 serial links, ensuring robust operation and compliance with industry standards.
- Assisting customers with system-level performance issues, providing technical guidance, troubleshooting, and support for integration and validation.
- Collaborating with internal teams on IP integration, ensuring seamless handoff and alignment with customer requirements and project timelines.
- Documenting methodologies, best practices, and technical findings for both internal knowledge sharing and customer-facing deliverables.
What You’ll Need:
- M.Sc. or Ph.D. in Electrical or Computer Engineering.
- Practical knowledge of digital communication engineering: Baseband Communication, Clock and data recovery, equalization, maximum likelihood sequence detection (MLSD) and Forward Error Correction (FEC).
- Proven Experience with Digital Communication blocks & system modeling in MATLAB/Simulink or similar tools.
- Expertise in Digital Signal Processing (DSP) including
-Low-power algorithm development, Fixed point design
-Linear and nonlinear equalization, and adaptive filtering
- Experience analyzing link budgets and optimizing NRZ and PAM4 high-speed serial links.
- Knowledge of high-speed serial data protocols: 10G/25G/56G/112G/224G Ethernet, OIF
- Understanding of Tx/Rx equalization techniques, CDR architecture, and loop dynamics.
Nice to have:
- Knowledge in Optical Communication
- Experience in high-speed analog CMOS circuit design.
- Hands-on experience with lab testing of high-speed serial links and correlating with simulation.
- Familiarity with Python, C/Verilog-A/’System Verilog’ for advanced modeling and verification.
Who You Are:
- Innovative, analytical, and detail-oriented with a strong sense of ownership and accountability.
- Excellent communicator, able to convey complex concepts to diverse audiences.
- Collaborative team player who thrives in multidisciplinary and multicultural environments.
- Adaptable and resilient, comfortable navigating fast paced and dynamic project requirements.
- Committed to continuous learning and staying current with industry advancements.
- Inclusive, respectful, and supportive of diverse perspectives and backgrounds.
The Impact You Will Have:
- Drive the development of industry-leading SerDes IP, enabling ultra-high-speed data transmission for next-generation SoCs and system solutions.
- Accelerate customers’ time-to-market by delivering robust, validated, and high-performance IP that integrates seamlessly into their products.
- Enhance product differentiation and competitiveness for Synopsys customers, reducing their risk and development cycles.
- Strengthen Synopsys’ leadership and reputation in the silicon IP market through technical excellence and customer-centric solutions.
- Mentor and share knowledge with peers, fostering a culture of learning, collaboration, and continuous improvement within the organization.
The Team You’ll Be A Part Of:
You will join a world-class R&D team at the forefront of high-speed SerDes IP development. The group is a dynamic mix of analog and digital designers, system architects, and hardware engineers, all committed to technical excellence and innovation. The team collaborates closely to solve complex technical challenges, deliver industry-leading solutions, and enable Synopsys customers to achieve their most ambitious goals. You’ll benefit from a culture that values knowledge sharing, mentorship, and continuous improvement.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
Requirements
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