Principal Design Verification Engineer
Synopsys
Ottawa, ON-
Number of positions available : 1
- Salary To be discussed
- Published on February 3rd, 2026
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Starting date : 1 position to fill as soon as possible
Description
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You Are:
You are an experienced verification engineer with at least 8 years in digital verification. You thrive in collaborative environments, enjoy mentoring others, and have a passion for solving complex technical challenges. You’re skilled in System Verilog, UVM, scripting, and bring a creative, systematic approach to problem-solving. Your strong communication skills and proactive mindset make you a valuable team player eager to deliver high-quality results.
What You’ll Be Doing:
- Define and build verification environments for IP-level designs using System Verilog and UVM.
- Apply advanced verification techniques for SerDes applications.
- Develop test cases, checkers, and coverage metrics.
- Provide technical leadership and mentor junior engineers.
- Collaborate with cross-functional teams globally.
- Drive end-to-end verification and continuous process improvement.
The Impact You Will Have:
- Ensure robust digital design verification and high product quality.
- Influence new product architectures and development strategies.
- Mentor and grow the engineering team.
- Accelerate project delivery by resolving verification challenges early.
- Enhance Synopsys’ leadership in digital verification.
- Foster a culture of innovation and collaboration.
What You’ll Need:
- Bachelor’s or Master’s in Electrical/Computer Engineering or related field; 8+ years of digital verification experience.
- Expertise in System Verilog, Verilog, or VHDL and UVM.
- Experience with coverage-driven RTL verification.
- Strong scripting and C/C++ programming skills.
- Ability to define verification plans and develop testbenches.
Who You Are:
- Self-motivated, collaborative, and a strong communicator.
- Creative, analytical, and adaptable to new challenges.
The Team You’ll Be A Part Of:
Join a high-performing engineering team focused on digital verification of leading-edge IP, collaborating across domains and geographies to deliver innovative solutions.
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
Requirements
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