High-Speed PHY Algorithms Lead

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced engineering leader with deep expertise in algorithm development for high-speed SerDes PHYs for calibration, adaptation, equalization and performance optimization. You thrive in multidisciplinary teams, excel at technical problem-solving, and are passionate about building robust solutions to complicated mixed-signal challenges from concept through hardware demonstration. You enjoy mentoring others, collaborating to solve complex issues, and clearly communicating technical insights to diverse audiences.

What You’ll Be Doing:

• Defining, documenting, and reviewing algorithms for SerDes PHY functions, with a focus on firmware and RTL implementation quality.
• Collaborating closely with architecture, analog, digital, firmware, and hardware teams to ensure the correctness and repeatability of SerDes algorithms across multiple protocols and standards.
• Coordinating feasibility and robustness studies for new algorithmic features in high-speed serial protocols such as Ethernet and PCIe.
• Driving cross-team integration and validation to guarantee deterministic accuracy and stability from simulation through hardware demonstration, including thorough corner-case and stress testing.
• Analyzing lab and field data to refine, debug, and enhance algorithm performance, resilience, and repeatability.
• Supporting system-level debug, root cause analysis, and escalations related to algorithm implementation in firmware or RTL.
• Mentoring and guiding junior team members in the development and validation of algorithms, fostering growth and knowledge sharing across the team.
• Serving as a key technical resource, communicating algorithm capabilities and limitations in both internal and customer-facing engineering forums.

The Impact You Will Have:

• Advance next-gen 224G/448G SerDes PHY performance and reliability.
• Deliver robust, high-quality calibration and adaptation features and overall PHY performance.
• Drive successful implementation, verification, and validation of algorithmic features across multidisciplinary engineering teams.
• Enhance technical excellence and knowledge sharing.
• Strengthen Synopsys’ leadership in high-speed PHY IP.

What You’ll Need:

• MSc+ in Electrical/Computer Engineering or related field.
• 8+ years in algorithm/signal processing for SerDes PHY or mixed-signal systems.
• MATLAB/Simulink, C, or Python expertise.
• Hands-on SerDes modeling and calibration experience.
• Strong troubleshooting and cross-team collaboration skills.

Who You Are:

• Technical leader and mentor.
• Strategic, analytical, and collaborative.
• Excellent communicator and problem-solver.

The Team You’ll Be A Part Of:

Join the High Speed SerDes PHY Architecture Team, a collaborative group dedicated to innovation in high-speed serial technology and robust algorithmic design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details on salary and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.