ASIC Digital Verification - Principal Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned verification leader, ready to drive technical excellence and inspire teams at the forefront of digital ASIC innovation. With over eight years of progressive experience in digital design and verification, you have a track record of delivering complex projects and scaling best practices across organizations. Your expertise in SystemVerilog/UVM and digital circuit design is matched by your ability to architect robust verification strategies and guide others in executing them. As a Principal Engineer, you naturally take ownership, providing technical direction while fostering a culture of collaboration, accountability, and continuous improvement. Colleagues look to you for mentorship, and you excel at elevating team performance through coaching and knowledge sharing. You are adept at communicating across disciplines and with stakeholders at all levels, ensuring alignment on priorities and objectives. Your leadership style is inclusive and empowering, encouraging innovation and adaptability within your team. Whether solving intricate design challenges or shaping verification methodologies, you are motivated by a desire to make a lasting impact on both products and people. You thrive in dynamic environments, embrace the responsibility of shaping future engineers, and are committed to upholding Synopsys’ standards of technical excellence and integrity.

• Leading the definition, development, and execution of advanced verification strategies for next-generation HBM products.
• Architecting complex testbenches and environments using SystemVerilog/UVM, setting standards for the broader team.
• Providing technical leadership in debugging, root cause analysis, and resolution of challenging testbench and design issues.
• Guiding and mentoring junior and senior engineers, fostering skill development and knowledge transfer within the team.
• Collaborating with design, architecture, and mixed-signal teams to ensure seamless integration and alignment across project phases.
• Driving process improvements, implementing automation and scripting (Python, Perl) to enhance verification productivity and reliability.
• Representing the verification function in cross-functional meetings, communicating progress, risks, and mitigation strategies to stakeholders.

• Shape the technical direction and verification methodologies for industry-leading HBM products.
• Elevate the capability and performance of the verification team through leadership and mentorship.
• Accelerate project timelines and improve product quality by implementing efficient, scalable verification solutions.
• Ensure rigorous verification standards, reducing risk and reinforcing Synopsys’ reputation for excellence.
• Drive cross-functional collaboration, aligning teams toward common goals and successful project outcomes.
• Serve as a role model and technical authority, inspiring the next generation of engineers at Synopsys.

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE).
• Minimum of 15 years of digital design and verification experience, with a demonstrated leadership track record.
• Expertise in architecting and developing verification environments using SystemVerilog and UVM.
• Advanced debugging skills for complex testbench and design issues.
• In-depth understanding of digital circuit design and verification methodologies.
• Strong scripting ability in Python or Perl for process automation.

PLEASE NOTE: If youlack technical depth or number of years of industry experience, please do not let this discourage you from applying. We are flexible with candidates that can demonstrate the attitude and aptitude to learn and develop with Team Synopsys.

• Visionary leader who inspires and empowers others to achieve excellence.
• Effective communicator and collaborator, comfortable influencing across teams and organizational levels.
• Mentor and coach, dedicated to the growth and development of your team.
• Strategic thinker, able to balance technical depth with project and business goals.
• Organized, self-motivated, and committed to continuous improvement and learning.

You will be part of an experienced mixed-signal design and verification team, targeting the next generation HBM products. Our team is composed of veteran digital and mixed-signal engineers who are committed to delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips. We foster a collaborative and dynamic environment that provides continuous training and professional growth opportunities. As a Principal Engineer, you will play a pivotal role in shaping both the technical and cultural direction of the team.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.