ASIC Digital Design, Principal Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a dynamic technical leader and visionary, recognized for your expertise and influence in the field of digital ASIC design. As a Principal Engineer, you are not only a master of RTL and mixed-signal design but also a respected mentor and thought leader within your organization and the wider industry. Your deep technical acumen is matched by your ability to set strategic direction, drive architectural decisions, and inspire teams to achieve excellence.

You approach challenges with a systems mindset, proactively identifying opportunities for innovation and process improvement. Your leadership extends beyond your immediate team, as you actively share knowledge, champion best practices, and foster cross-disciplinary collaboration across global teams. You are skilled at distilling complex technical concepts for diverse audiences, influencing stakeholders, and driving consensus on critical design and architectural matters.

Your career is distinguished by a track record of delivering industry-leading solutions in high-speed, low-power digital and mixed-signal domains. You thrive in high-visibility roles, guiding projects from concept through successful delivery, and shaping the roadmap for future technologies. Above all, you are passionate about developing talent, building inclusive teams, and cultivating a culture of innovation and continuous learning.

• Providing technical and architectural leadership for the HBM PHY RTL team, setting the vision and direction for complex, high-performance memory interface projects.
• Driving the definition, development, and delivery of industry-leading RTL designs that meet stringent quality, performance, and power requirements.
• Mentoring, coaching, and developing engineering talent within the team and across the organization, fostering a culture of excellence and collaboration.
• Leading technical reviews, design audits, and architecture discussions, ensuring robust solutions and adherence to best practices.
• Influencing and aligning cross-functional teams-including analog, mixed-signal, layout, and verification groups-on technical strategy and project execution.
• Promoting and implementing automation, process improvements, and innovative methodologies to enhance productivity and design quality.
• Representing Synopsys as a technical authority in customer engagements, industry forums, and standards bodies.
• Authoring and reviewing key technical specifications, white papers, and design documentation.

• Elevate the technical capabilities and reputation of Synopsys’ HBM PHY IP portfolio through visionary leadership and innovation.
• Shape and influence the strategic direction of memory interface technologies, positioning Synopsys as a market leader.
• Drive cross-team synergy and alignment, resulting in accelerated project delivery and higher quality outcomes.
• Mentor and empower the next generation of engineers, leaving a lasting legacy of technical excellence and innovation.
• Enhance customer success and satisfaction through proactive technical guidance and problem resolution.
• Contribute to industry standards and thought leadership, amplifying Synopsys’ voice in the semiconductor ecosystem.

• 10+ years of proven experience in digital ASIC/RTL design, with significant leadership in complex, high-speed, and low-power systems.
• Expert-level proficiency in SystemVerilog, Verilog, and advanced scripting for automation (Python, Perl, TCL, etc.).
• Extensive experience architecting and delivering ASIC/IP in leading-edge process nodes, including physical implementation and DFT/DFM flows.
• Demonstrated ability to lead architecture definition, technical reviews, and multi-disciplinary project teams.
• Exceptional written and verbal communication skills, with experience authoring technical papers, specifications, and presenting to executive and customer audiences.
• Deep knowledge of high-speed interface standards (HBM, DDR, UCIe) and physically aware synthesis methodologies.
• Experience modeling analog and mixed-signal circuits and debugging complex hardware issues.

• Visionary leader with a collaborative and inclusive leadership style.
• Strategic thinker skilled at balancing short-term project goals with long-term technical vision.
• Inspirational mentor, passionate about developing people and teams.
• Excellent communicator, influencer, and consensus builder across technical and non-technical stakeholders.
• Proactive, adaptable, and resilient in the face of complex challenges.
• Committed to continuous learning, innovation, and fostering a diverse, high-performing engineering culture.

You will lead and inspire a high-performing RTL design team dedicated to advancing the state-of-the-art in HBM PHY IP. The team is collaborative, globally distributed, and highly respected for its technical depth and innovation. As Principal Engineer, you will play a pivotal role in shaping team culture, driving technical decisions, and ensuring the successful delivery of industry-defining solutions.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.