Master's Intern: ASIC Digital Verification

Master's Intern: ASIC Digital Verification

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance chips that help build a healthier, safer, and more sustainable world.

Mission Statement: Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive-both at work and beyond.

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide-and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Key Program Facts:

• Duration: 8 to 16 months
• Location: Flexible (Toronto, Mississauga, Markham, Ottawa)
• Working Model: Hybrid (2-3 days/week in office)
• Start Date: Fall 2025

What You’ll Be Doing:

• Defining and tracking Verification Testplans.
• Designing and writing constrained-random SystemVerilog testbenches using a Verification Methodology such as UVM (Universal Verification Methodology).
• Creating and examining Functional Coverage.
• Writing SystemVerilog assertions.
• Debugging RTL and gate-level simulation failures.
• Firmware Debug.
• Bug Tracking using Software Tools such as Jira.
• Code Coverage Analysis.

What You’ll Need:

• Prior industry experience in UVM is mandatory - please highlight in your resume.

• Experience in writing testcases in Verilog and System Verilog.
• Experience in debugging complex testbench and design related issues.
• Good understanding of ASIC Digital Design.
• Familiarity with scripting languages (Python or Perl).

Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.